The present invention relates to nonvolatile erasable programmable memories and more specifically, techniques for organizing or laying out the memory cells on the integrated circuit.
Memory and storage is one of the key technology areas that is enabling the growth in the information age. With the rapid growth in the Internet, World Wide Web (WWW), wireless phones, personal digital assistants (PDAs), digital cameras, digital camcorders, digital music players, computers, networks, and more, there is continually a need for better memory and storage technology. A particular type of memory is nonvolatile memory. A nonvolatile memory retains its memory or stored state even when power is removed. Some types of nonvolatile erasable programmable memories include as Flash, EEPROM, EPROM, MRAM, FRAM, ferroelectric, and magnetic memories. Some nonvolatile storage products include CompactFlash (CF) cards, MultiMedia cards (MMC), Flash PC cards (e.g., ATA Flash cards), SmartMedia cards, and memory sticks.
A widely used type of semiconductor memory storage cell is the Flash memory cell or floating gate memory cell. There are other types of memory cell technologies such as those mentioned above. Flash and floating gate memory cells are discussed as merely an example. The discussion in this application would also apply to other memory technologies other than Flash and floating gate technology with the appropriate modifications. The memory cells are configured or programmed to a desired configured state. In particular, electric charge is placed on or removed from the floating gate of a Flash memory cell to put the cell into two or more stored states. One state is a programmed state and another state is an erased state. A Flash memory cell can be used to represent at least two binary states, a 0 or a 1. A Flash memory cell can also store more than two binary states, such as a 00, 01, 10, or 11; this cell can store multiple states and may be referred to as a multistate memory cell, a multilevel, or multibit memory cell. This allows the manufacture of higher density memories without increasing the number of memory cells since each memory cell can represent more than a single bit. The cell may have more than one programmed state. For example, for a memory cell capable of representing two bits, there will be four programmed states.
Despite the success of nonvolatile memories, there also continues to be a need to improve the technology. It is desirable to improve the density, speed, durability, and reliability of these memories. It is also desirable to reduce power consumption and reduce the cost per bit of storage.
As can be appreciated, there is a need for improving the performance and reducing the power consumption of nonvolatile memories. In particular, by arranging and laying out the memory cells of an integrated circuit so bitlines of the memory cells are segmented, this will reduce noise between bitlines and improve the performance and reliability, and reduce power consumption.
The invention provides an organization for memory cells of an integrated circuit where metal bitlines are segments In a specific embodiment, the memory cells are nonvolatile memory cells such as floating gate, Flash, EEPROM, and EPROM cells. The bitlines for the memory cells are strapped to metal (e.g., metal-2) and this metal is segmented. The individual segments may be selectively connected to voltages as desired to allow configuring (e.g., programming) or reading of the memory cells. By dividing the metal bitlines into segments, this reduces noise between bitlines and improve the performance and reliability, and reduce power consumption because the parasitic capacitances to be charged or discharged are reduced compared to a long metal bitline (i.e., where all the segments are connected together and operated as one). Between the segments are at least two pass gates (e.g., three pass gates). One pass gate connects or disconnects two segments together. For each of the segments, there is a pass gate the connects or disconnects the segment to a supply line. The supply line will be selectively connected to a voltage such as VPP or VSS (ground).
Although the invention has been described with respect to metal bitlines, the invention may also be applied to other metal lines, such as metal wordlines, to obtain similar benefits for those lines. However, the invention, is particularly effective for metal bitlines because the bitlines are raised to a VPP (e.g., 6.5 volts) for programming. And switching from 0 volts to VPP is a significant enough swing that much noise is generated during the switch and dynamic power is consumed.
In an embodiment, the invention is an integrated circuit including an array of nonvolatile memory cells, wherein the array includes a metal bit line divided into a first segment and a second segment. In particular, the metal bit line is connected or strapped to the bit line node of a column of memory cells in the array. A first pass gate is connected between the first and second segment. A second pass gate is connected between the first segment and a supply line. For example, the supply line may be VPP or VSS. In one implementation, the first and second pass gates are NMOS transistors. In another implementation, the first and second pass gates are CMOS pass gates.
In operation, the supply line is selectively connected to VPP or VSS, where VPP is a programming voltage level above a VCC level for the integrated circuit. VSS is ground. The invention may further include a third pass gate connected between a VPP line and the first supply line, and a fourth pass gate coupled between a VSS line and the first supply line. In a first mode of operation, the first pass gate is on and the second pass gate is off. In a second mode of operation, the first pass gate is off and the second pass gate is on.
Furthermore, the memory cells may be floating gate memory cells, which include Flash, EEPROM, or EPROM memory cells. The memory cells may be multistate memory cells. Each memory cell is capable of storing a plurality of binary bits of data.
In another embodiment, each segment can have its own dedicated connection to VSS and VPP. Specifically, a second pass gate is connected between the first segment and a first supply line. And, a third pass gate is connected between the second segment and a second supply line. For example, the first supply line may be VPP, and the second supply line may be VSS, or vice versa. In one implementation, the first, second, and third pass gates are NMOS transistors. In another implementation, the first, second, and third pass gates are CMOS pass gates.
In operation, the first supply line is selectively connected to VPP or VSS, where VPP is a programming voltage level above a VCC level for the integrated circuit. The second supply line is selectively connected to VPP or VSS, wherein VPP is a voltage level above a VCC level for the integrated circuit. VSS is ground. The invention may further include a fourth pass gate connected between a VPP line and the first supply line, and a fifth pass gate coupled between a VSS line and the first supply line.
In a first mode of operation, the first pass gate is on and the second and third pass gates are off. In a second mode of operation, the first pass gate is off and the second pass gate is on. Further in the second mode of operation, the third pass gate is off.
Other objects, features, and advantages of the present invention will become apparent upon consideration of the following detailed description and the accompanying drawings, in which like reference designations represent like features throughout the figures.